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MRF49XA
REGISTER 2-9:
RXFIFOREG: RECEIVER FIFO READ REGISTER (POR: 0xB000)
W-1
W-0
W-1
W-1
W-0
W-0
W-0
W-0
CCB<15:8>
bit 15
bit 8
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
RXDB<7:0>
bit 7
Legend:
r = reserved bit
bit 0
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-8
bit 7-0
CCB<15:8>: Command Code bits
The command code bits ( 10110000b ) are serially sent to the microcontroller to identify the bits to be
written in the RXFIFOREG.
RXDB<7:0>: Receiver Data Byte bits
These are the recovered data bits stored in the FIFO. The controller can read 8 bits from the receiver
FIFO over the SPI bus. The FIFOEN bit (GENCREG<6>) should be set to receive these bits.
? 2009-2011 Microchip Technology Inc.
Preliminary
DS70590C-page 31
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